Display Interface Quick Reference: SPI to eDP

This is the fast lookup for display interfaces: one table of operating envelopes, plus the handful of accuracy notes that keep you out of trouble. It does not re-teach the interfaces. For what each one is and how it works, see display interfaces explained; for choosing one against host support, cable length, cost, and power, see choosing a display interface. This page is the cheat sheet those two earn.

Part of the Reference knowledge hub.

An interface ladder of rising steps from left to right: I-squared-C at 2 wires driving 128 by 64, then SPI at 4 to 6 wires driving QVGA, then MCU parallel at 13 to 28 wires to WVGA, then RGB or DPI at 22 to 40 wires to about 1024 by 600, then LVDS at 8 to 20 wires reaching WXGA to Full HD, then MIPI DSI at 4 to 10 wires to 4K, then eDP at 6 to 12 wires beyond 4K, grouped as serial single-ended, parallel single-ended, and differential serial, with a note that past RGB the differential links carry more pixels over fewer wires.

The interfaces at a glance

Wire counts are interface signal lines only (data, clock, sync, control), not power, backlight, or touch. Bandwidth and resolution ceilings are realistic ranges for custom TFT and OLED modules, not hard maxima.

Interface	Signal type	Wires	Typical bandwidth	Resolution ceiling	Color depth	Typical use
I²C	Serial, single-ended, 2-wire bus	2	100 kHz to 3.4 MHz	OLED 128×64, character	Mono / 1–4 bpp	Tiny status OLEDs, character LCDs, shared bus
SPI	Serial, single-ended	4–6	~1 to 80 Mbit/s	QVGA, pushes to 480×320	Mono, RGB565/666	Small mono or low-res color, wearables, low pin count
MCU parallel (8080 / 6800)	Parallel, single-ended + GRAM	13–28	Moderate	QVGA to ~WVGA	RGB565 / RGB666	Small to medium TFT with on-glass RAM; UI, not video
RGB / DPI	Parallel, single-ended, per-pixel	22–40	~0.1 to 0.5 Gbit/s	~800×480 to 1024×600	RGB565/666/888	Medium TFT, video; host needs an RGB controller
LVDS, single channel	Differential serial	8–10	~0.4 to 1 Gbit/s/pair	up to WXGA 1366×768	18 or 24-bit	Industrial and medium panels, noise immunity, cable runs
LVDS, dual channel	Two LVDS links (odd/even)	16–20	~2× single channel	1920×1080 / 1200 and up	18 or 24-bit	Larger, higher-res industrial and medical
MIPI DSI	Differential serial, 1–4 lanes	4–10	~1 to 2.5 Gbit/s/lane	720p to 4K	18/24/30-bit	Compact high-res modules; best bandwidth per wire
eDP	Differential serial, packetized	6–12	1.62 to 8.1 Gbit/s/lane	1080p to 4K+	18/24/30-bit	Large, high-res panels; laptops, all-in-ones, high-end HMI

The frame-buffer divide

The single most confused point, because two very different architectures both get called “parallel.” SPI, I²C, and MCU-parallel panels carry an on-glass driver IC with its own display RAM (GRAM): the host writes the image once, and the driver holds and refreshes it, so a modest MCU can drive the panel. RGB / DPI panels have no on-glass frame buffer. The host must stream every pixel of every frame continuously, clocking out DCLK, HSYNC, VSYNC, and DE, which means it needs a real RGB controller and framebuffer memory of its own. A GRAM panel and an RGB panel are not interchangeable even at the same resolution, so confirm which one a “parallel” panel actually is before you design the host around it.

Serial differential vs parallel single-ended

The other split in the table is electrical. I²C, SPI, MCU-parallel, and RGB are single-ended: each signal is one wire referenced to ground. LVDS, MIPI DSI, and eDP are differential serial: each signal is a pair whose two wires swing against each other, which is what lets them run at gigabit rates, tolerate longer cables, and throw off less noise. That is why the ladder inverts near the top: MIPI DSI moves more pixels than RGB over far fewer wires, because a few fast differential lanes beat a wide slow bus. The cost is that the host must speak the serial protocol, or carry a bridge IC that does. Treat every resolution ceiling as practical bandwidth at a normal frame rate, not a physical wall; sources disagree on the exact tops precisely because they depend on frame rate and signal integrity.

Picking a row

Read one row as one interface’s envelope, and move down as the panel grows: I²C or SPI for tiny, SPI or MCU-parallel for small GRAM color panels, RGB for medium video, LVDS for medium-large industrial with a cable, MIPI DSI for compact high-res, eDP for large high-res. The router below is the lookup; the trade-offs behind it, host support, cable length, cost, and power, live in choosing a display interface.

A router mapping panel and content to interface: tiny status OLED or character LCD to I-squared-C or SPI; small color TFT for UI and still images to SPI or MCU parallel with GRAM; medium TFT for video and motion to RGB or DPI; medium-large industrial with a cable run to LVDS; compact high-res module to MIPI DSI; and large high-res panel to eDP, with a note that every ceiling is practical bandwidth at a normal frame rate, not a hard wall, and to confirm against the panel timing.

On a custom module the interface is an option, not a fixed attribute of the glass. The same panel can often be offered SPI, MCU-parallel, or RGB depending on the driver IC, and Orient Display can integrate a driver with built-in GRAM so a low-end MCU drives a panel that would otherwise need a full RGB controller. Where host and panel speak different interfaces, a bridge IC (MIPI-to-RGB, RGB-to-LVDS, MIPI-to-eDP) lets you keep the existing processor. For the units on these panels see display units and measurements, and to match an interface to a real part on the TFT and LCD lines.